1. Field of the Invention
The invention relates to a semiconductor integrated circuit, specifically relates to an output buffer circuit and its peripheral circuit which improve output characteristics of a signal from a semiconductor integrated circuit (IC).
2. Description of the Prior Art
An output buffer circuit is usually equipped at an output portion of IC for amplifying a feeble IC output signal to a level which is large enough to drive an outside load circuit. The driving current of the output buffer is decided by a size of a transistor. Therefore, in a conventional buffer design, the transistor size is decided when designing pattern layout of the transistors by predicting an outside load capacity which is connected to the buffer in order to obtain the buffer capacity which is enough to provide the current to the outside load.
According to speeding-up and up-sizing of recent electronic apparatus such as personal computers, operation speed and driving current of the output buffer circuit equipped in IC is required to increase higher and larger, respectively. Further, as IC is applied to electronic equipments widely, the buffer circuit is required to correspond to a various kinds of load capacities. But, in the past, the driving current of the output buffer has been decided at the time of pattern layout design, as described above. Therefore, it is difficult to set and decide the most suitable driving current of the output buffer in response to the load of electronic equipments such as personal computer board which is added later to the electric apparatus.
In recent years, as shown in FIG. 21, electronic equipments such as a personal computer are becoming to use systems which add an extension 14 like RAM card or a ROM card at a later time, or systems which are compatible with many kinds of power supplies which are switched between ac power supply and dc power supply like battery.
In such extension, when adding such extension 14 to IC 11 using a connector 13, it is required to provide a bus driver 12 between a connector 13 and the IC 11 which provides current enough to additional load capacity, which leads to a large size and a high cost of apparatus. In other words, buffer capacity of such systems is designed in consideration with an additional load capacity which is added later on. If the additional load capacity exceeds a predetermined designed value, delay time of providing current increases and then transmission errors increase. Also, in case there is no additional load capacity, power supply voltage of the system varies by switching current between ac power supply and dc power supply like battery, which also causes transmission errors.
In case of setting a driving current of the buffer rather higher in consideration with a high-speed operation system so that IC 11 is compatible with many kinds of power supplies, there is some problem that errors occur by change of power supply since the driving current is more than a necessary value if the buffer is used in a low speed operation system. On the contrary, in case of setting a driving current of the buffer rather lower in consideration with a low-speed operation system, there is some problem that delay time of buffer becomes too large if the buffer is used in a high speed operation system, where the system does not operate at a desired operational speed. Therefore, it is required to change driving current of a buffer to an adequate one when a load capacity connected to the buffer is not appropriate.
As a solution for such problems, there is a method proposed in a laid-open Japanese patent publication No. 6-311016. As shown in FIG. 22, the method supplies an appropriate load current to the load connected to terminal 16 by switching a switching circuit 18 by the control circuit 19 so that at least one of buffers (1)-(n) becomes conductive which is connected in parallel to a terminal 15 connected to CPU.
Although the output buffer circuit constructed described above may set and change a driving current by a signal from a control circuit, a complicated procedure for setting the number of output buffer circuit to be switched and a circuit diagram of control circuit. The procedure further is needed to consider maximum load capacity and minimum load capacity so that errors may not be occurred by a change of power sources and also an operation speed required in IC may be satisfied in the system.
It is common that delay time of the buffer defined on the semiconductor substrate varies by a voltage change of power source which supplies current to IC or by a temperature variation in an environment where IC is used. Therefore, in a conventional circuit shown in FIG. 22, there is a problem that delay time change is caused by temperature variation in an environment and then a signal input timing to an IC of next stage, which leads to a error of system.
Further, in the buffer circuit shown in FIG. 22, there is another problem that a big area is needed for forming a plurality of output buffer circuits on the surface of an IC.
It is an object of the present invention to provide an output buffer circuit which solves such problems. The buffer circuits, having driving current regulating function incorporated into an IC at a design stage, is controlled automatically and appropriately according to a load characteristics when an electronic equipment is used. The present invention can provide a small area buffer circuit on IC and also is hardly affected even if the load capacity is changed, even if an IC power supply is a multi-power supply type, or if power supply voltage and temperature varies.